1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device which has non-volatile memory cells and which is especially suitable for being integrated in a semiconductor chip together with a peripheral logic circuit.
2. Description of the Related Art
Recently, on a user side constituting a semiconductor system, there increase demands for a non-volatile semiconductor memory device which is inexpensive and, capable of programming data after a semiconductor chip is manufactured. Such a non-volatile semiconductor memory device is required to be integrated in a semiconductor chip together with a central processing unit (CPU) or a micro processor unit (MPU) in order to assure a higher level of security.
As a non-volatile semiconductor memory device capable of electrical erasure, there is known such a device that a transistor having a stacked gate structure included of a control gate electrode and a floating gate electrode is used as a memory cell.
The non-volatile semiconductor memory device using the transistor having such a stacked gate structure is known to have a high reliability. Such a non-volatile semiconductor memory device, however, has inherent specifications, an element structure, and manufacturing processes and so has poor compatibility with the other logic products. Therefore, this type of non-volatile semiconductor memory device gives rise to a great increase in number of steps and costs if it is to be integrated in the same semiconductor chip together with a peripheral logic circuit such as a CPU or an MPU.
As a non-volatile semiconductor memory device that can be easily integrated in the same semiconductor chip together with the peripheral logic circuit, there is conventionally known one such as described in, for example, “A Non-Volatile Memory Device with True CMOS Compatibility” by A. Bergemount et al., Non-Volatile Semiconductor Memory Workshop, pp. 86-89, 2000.
A cross-sectional structure of a memory cell described in this reference is shown in FIG. 1 and an equivalent circuit of a memory array in which this plurality of memory cells of FIG. 1 are arranged is shown in FIG. 2.
As shown in FIG. 1, in a P type semiconductor substrate (P-sub) 61, a plurality of N type wells (only one of which is shown in the figure) 62 are formed. In each of the plurality of N type wells 62, a source region 63 and a drain region 64 which are made of a P+ diffusion layer are formed. Further, a gate electrode 65 is formed on the substrate between the source and drain regions, to make up a cell transistor 66 constituted of a P-channel MOS transistor in each of the N type wells 62. The gate electrode 65 of the cell transistor 66 is not electrically connected anywhere so as to be in a floating potential state.
In each N type well 62, a contact region 67 made of an N+ diffusion layer is formed which serves to make contact with the N type well. The contact region 67 is connected together with the source region 63 to a bit line BL. Further, the drain region 64 of the cell transistor is connected to a ground-potential node via a selection transistor 68 constituted of an N-channel MOS transistor. A gate electrode of the selection transistor 68 is connected to a word line WL.
The memory cell shown in FIG. 1 is formed many, to form a memory cell array shown in FIG. 2. In the memory cell array, the respective pluralities of word lines WL and bit lines BL extend in such a manner that they may cross. At each intersection of each word line WL and each bit line BL is there arranged each memory cell MC. Each memory cell MC has such a configuration that the cell transistor 66 whose gate electrode is not electrically connected anywhere so as to be in the floating potential state as described above and the selection transistor 68 are connected in series. It is to be noted that a region enclosed by a broken line in FIG. 2 corresponds to the N type well 62 in FIG. 1.
In the non-volatile semiconductor memory device, after a semiconductor chip is manufactured, an entire surface of the chip is irradiated with an ultraviolet light, to initialize the gate electrodes of the cell transistors 66 of all of the memory cells MC into a charge-less state so that the cell transistors 66 may have a predetermined constant negative threshold value.
To write data, the selected bit line BL is supplied with a voltage of, for example, 5V or so. This causes the N type well 62 connected to the selected bit line BL to be set to 5V or so simultaneously. Further, only the selected word line WL is provided with the “H” level potential to turn ON the selected transistor 68, so that 0V is transmitted to the P+ diffusion layer, which is the drain region 64 of the cell transistor 66. In this case, the other word lines are connected to the ground level of 0V and the selection transistor 68 is turned OFF. In the selected cell transistor 66 placed at the intersection of the selected bit line and the selected word line, the N type well 62 and the source region 63 are each set to 5V or so, and the drain region 64 is set to 0V.
Upon application of the ultraviolet light, the threshold value of the cell transistor 66 is negative, so that the cell transistor 66 is in the ON state to flow a current between the drain region 64 and the source region 63, part of which current provides hot electrons, which pass through a gate insulation film of the cell transistor 66 and are injected into the gate electrode 65. This causes the threshold voltage of the cell transistor 66 to rise and turn positive. This state is defined, for example, as a “0” storage state.
In the cell transistor 66 into which no electrons are desired to be injected, the bit line BL connected to the cell transistor is set to 0V in potential beforehand so that the negative threshold voltage upon the application of the ultraviolet light may be maintained unchanged. This state is defined, for example, a “1” storage state.
To read the data, the selected bit line BL is supplied with a predetermined positive-polarity potential and the selected word line WL is also supplied with the predetermined positive polarity potential, to turn ON the selected transistor 68. If the gate electrode 65 of the cell transistor 66 has no electrons yet injected therein and stays as exposed to the ultraviolet light, the threshold voltage of the cell transistor 66 is of a negative polarity. Therefore, the cell transistors 66, which stays,as exposed to the ultraviolet light, is turned to ON state, so that the current starts flowing through the bit line BL.
On the other hand, if the gate electrode 65 has electrons injected and data written beforehand and so its threshold voltage is shifted to the positive polarity, its cell transistor 66 is turned OFF, so that no current flows through the bit line BL.
In such a manner, when the data is read, in accordance with whether the data is written or not, the cell transistor is in the ON or OFF state respectively, in accordance with which in turn, the current flows or does not flow through the bit line BL respectively. Whether the current flows through the bit line BL or not is decided by a sense-amplifier, to detect whether the data is “0” or “1”.
The non-volatile semiconductor memory device, however, has the following problems. The first problem is that it is not capable of electrical erasure. That is, it is designed to erase the data by applying the ultraviolet light and so needs to use a package provided with a window fitted with quartz glass which transmits the ultraviolet light, which package, however, is very expensive.
The second problem is that the N type well needs to be independently provided for each memory cell, so that the cell becomes large in area. Therefore, the memory device having such a large bit capacity cannot be formed in a semiconductor chip.
Therefore, there has conventionally been a demand for solving these problems.